The continual demand to enhance integrated circuit (IC) performance has resulted in a reduction of semiconductor device geometries, and continual efforts to operate semiconductor devices over a wide range of voltages. In particular, for semiconductor devices such as lateral double-diffused metal oxide semiconductor (LDMOS) transistors, or drain extended MOS (DEMOS) transistors used as high voltage devices (e.g., about 20 Volts and higher), it is often necessary to simultaneously optimize several electrical parameters. These parameters can include the breakdown voltage (BDV), specific on-resistance (Rsp=on-state resistance in linear regime times device area) and switching speed (e.g., as represented by the Rsp*Qgd quality factor, where Qgd is the gate-to-drain charge). Compromises in the value of one or more of these parameters, or to the dimensions of the device, have to be made in order for the device to work in its intended safe operating region.